1. Field of the Invention
The present invention relates to a pattern generating apparatus for an IC tester destined for testing an electronic device such as an integrated circuit or IC device (hereinafterster referred to as DUT in an abbreviation of device under test). More particularly, the invention concerns a pattern generating apparatus which generates a driver pattern applied to a DUT and an expected pattern to be utilized as a reference pattern for comparison with the output pattern produced by the DUT in response to the input driver pattern, wherein decision of the DUT as to the performance thereof is made on the result of the comparison.
2. Description of the Prior Art
For having a better understanding of the present invention, description will first be made of a typical one of the hitherto known relevant techniques by referring to FIG. 2 of the accompanying drawings.
In the figure, a reference numeral 3 denotes an input/output port (hereinafter referred to simply as IO port), 4 denotes a CPU (an abbreviation of central processing unit), 6 denotes a pattern generator, and a reference numeral 7 denotes a decision unit. With the arrangement shown in FIG. 2, an IC tester for testing a pin of an IC DUT (IC device under test) 5 is realized.
The pattern generator 6 is composed of a pattern memory 6A, an input/output mode memory or IO memory 6B, a driver pattern generating circuit 6C and an expected pattern generating circuit 6D. The pattern memory 6A produces an output of one bit which is applied to both the driver pattern generating circuit 6C and the expected pattern generating circuit 6D. The IO memory 6B produces an output of one bit which is applied only to the driver pattern generating circuit 6C. The driver pattern generating circuit 6C samples the output of the pattern memory 6A, wherein the sampled output of the latter being converted into a waveform required for testing the DUT 5 and subsequently applied to the IO port 3. In this conjunction, the CPU 4 has placed various modes of waveform in the driver pattern generating circuit 6C in precedence to execution of the test. The driver pattern generating circuit 6C samples the output signal of the IO memory 6B, the sampled signal being inputted to the IO port 3. On the other hand, the expected pattern generating circuit 6D samples the output signal of the pattern memory 6A, wherein the sampled signal is supplied to the decision unit 7 as the expected pattern (reference pattern).
The DUT 5 is connected to an IO terminal of the IO port 3. When the IO pattern produced by the driver pattern generating circuit 6C is logic "1", the IO terminal is set to the input (I) mode, allowing the IO port 3 to transmit the driver pattern to the DUT 5. On the other hand, when the IO pattern is logic "0", the IO terminal is set to the output (O) mode, whereby the output pattern generated by the DUT 5 is transmitted to the decision unit 7.
The pin of the DUT 5 under test can be selectively set to I-mode, O-mode and Z-mode. In the I-mode of the pin, the DUT 5 is set to the input mode. In the O-mode, the DUt 5 is set to the output mode, while the DUT 5 is set to a high-impedance state in the Z-mode.
The decision unit 7 compares the expected pattern with the output pattern of the DUT 5 to make decision as to whether the DUT 5 is to be satisfactory or not.
A circuit configuration of the decision unit 7 is shown in FIG. 3. In the figure, reference characters 7A and 7B denote comparators, respectively, and 7C denotes a decision circuit. Further, symbols V.sub.OH and V.sub.OL denote reference potentials of high and low levels, respectively, utilized for comparison.
The comparator 7A compares the high potential of the DUT 5 with the high reference potential V.sub.OH, the result of the comparison being supplied to the decision circuit 7C. On the other hand, the comparator 7B compares the low reference voltage V.sub.OL with the low potential of the DUT 5, wherein the result of the comparison is applied to the decision circuit 7C. The decision circuit 7C in turn compares the expected pattern with the output of the comparator 7A when the expected pattern is logic "1", while the expected pattern is compared with the output of the comparator 7B in case the expected pattern is logic "0". In this way, decision is made as to whether the DUT 5 is to be satisfactory or not.
Next, operation of the pattern generating apparatus shown in FIG. 2 will be described by referring a timing/waveform diagrams shown in FIG. 4.
FIG. 4 illustrates at (a) a timing signal including timing pulses S1, . . . , S6, . . . . This timing signal (a) is supplied to both the driver pattern generating circuit 6C and the expected pattern generating circuit 6D to be used for sampling the outputs of the pattern memory 6A and the IO memory 6B, respectively. Accordingly, the pulse repetition period of the timing signal (a) shown in FIG. 4 at (a) determines the repetition period of the driver pattern and the expected pattern.
Shown at (b) in FIG. 4 is an output waveform of the pattern memory 6A which waveform assumes logic level "1" in response to the timing pulse signal S1, S2 and S5, respectively.
There is shown at (c) of FIG. 4 an output waveform of the IO memory.
Finally, FIG. 4 shows at rows (d) to (g) four different waveforms of the driver pattern which may be selectively applied to the DUT 5. For selecting one of the waveforms (d) to (g) shown in FIG. 4, the CPU 4 sets a waveform mode corresponding to a selected one of the four waveforms (d) to (g) at the driver pattern generating circuit 6C in precedence to execution of the test. Accordingly, when the DUT 5 is being tested, the driver pattern generating circuit outputs 6C continuously the driver pattern of the selected one waveform.
Shown in FIG. 4 at (d) is a waveform which results from the sampling of the waveform shown at (d) in FIG. 4 by the timing signal shown at (a) in FIG. 4. The waveform shown at (e) in FIG. 4 corresponds to the inversion of the waveform shown in FIG. 4 at (d).
Shown at (f) in FIG. 4 is a waveform which is obtained through a logic operation of the waveform shown at (c) in FIG. 4, while the waveform shown at (g) corresponds to the inversion of the waveform shown at (f) in FIG. 4.
Shown in FIG. 4 at (h) is an output waveform of the expected pattern generating circuit 6D which is derived by sampling the waveform shown at (b) with the timing signal shown at (a) in FIG. 4.
The decision unit 7 compares the expected pattern shown at (h) in FIG. 4 with the output of the comparator shown in FIG. 3 which corresponds to the expected pattern (h) to thereby make decision as to whether the DUT 5 is acceptable or not.
As will be seen from the above description, the hitherto known apparatus suffers difficulties mentioned below.
When it is desired that the driver pattern of another waveform is to be applied to the DUT 5 during a period intervening between the timing pulses S1 and S2, the CPU 4 has to set the waveform mode to replace the current one at the driver pattern generating circuit 6C every time one test is completed.
Further, when there is necessity of inhibiting the decision as to the acceptability of the DUT 5 in the hitherto known apparatus, a memory destined for inhibiting such decision has to be additionally incorporated in the apparatus.